Semiconductor technology continues to scale to ever smaller transistor sizes to include more and more transistors in a single integrated circuit device. This geometric scaling down of transistor dimensions results in increasingly higher electric fields in the transistors. One consequence of these higher electric fields is higher supply currents yielding higher dissipated power. One way to counter this increase in supply currents is to use lower power supply voltages to keep the dissipated power within reasonable limits. With lower power supply voltages, voltage drops in the on-package and on-chip portion of a power distribution network (PDN) are becoming dominant and are a significant detractor to performance. The lower supply voltages and higher supply currents transiting through the package, together with chip resistive losses, result in ever-increasing variations of supply voltages received at the different circuit blocks within a device. These variations limit the performance that can be guaranteed by design, because an externally supplied voltage level may be sufficient for one circuit block, while the same externally supplied voltage level may be inadequate for what another circuit block requires.